GBZ80

The Game Boy uses a processor called the Sharp LR35902 which has many similarities to the Intel 8080 and Zilog Z80 processors. On the DMG Game Boy, the processor operates at about 4.19MHz, but the CGB (Game Boy Color) console allows for a double speed mode with allows the processor to run at about 8.38MHz.

GBZ80 Instructions

• ADC
• ADD
• AND
• BIT
• CALL
• CCF
• CP
• CPL
• DAA
• DEC
• DI
• EI
• HALT
• INC
• JP
• JR
• LD
• LDH
• NOP
• OR
• POP
• PUSH
• RES
• RET
• RETI
• RL
• RLA
• RLC
• RLCA
• RR
• RRA
• RRC
• RRCA
• RST
• SBC
• SCF
• SET
• SLA
• SRA
• SRL
• STOP
• SUB
• SWAP
• XOR

GBZ80 Status Flags (F)

• - (bit 0) - Always 0
• - (bit 1) - Always 0
• - (bit 2) - Always 0
• - (bit 3) - Always 0
• CF (bit 4) - Carry Flag
• HF (bit 5) - Half Carry Flag
• NF (bit 6) - Negative Flag (last arithmetic operation was SUB, SBC, CP, or 8-bit DEC)
• ZF (bit 7) - Zero Flag

GBZ80 Number Bases

• 10 - Decimal number 10
• $0A - Hexadecimal number 0x0A
• %00001010 - Binary number 0b00001010

GBZ80 Opcode Placeholder Values

• cc - Condition code (C = Carry Flag Set, NC = Carry Flag Clear, Z = Zero Flag Set, NZ = Zero Flag Clear, C = Carry Flag Set)
• r8 - 8-bit value at register (A, B, C, D, E, H, L)
• r16 - 16-bit value at combined register, where the first register is the High byte and the second register is the Low byte (BC, DE, HL)
• s8 - 8-bit signed number
• u3 - 3-bit unsigned number (0 through 7)
• u8 - 8-bit unsigned number
• u16 - 16-bit unsigned number (assembly code will use big-endian numbers, but machine code will encode the number in little-endian form)
• vec - Reset Vector ($00, $08, $10, $18, $20, $28, $30, $38)
• A - 8-bit A register
• AF - 16-bit value that is the A register and Status Flags (F) combined, where the A register is the High byte and the Status Flags (F) byte is the Low byte
• HL - 16-bit combined register HL, where the H register is the High byte and the L register is the Low byte
• PC - 16-bit value of Program Counter
• SP - 16-bit value of Stack Pointer
• [C] - 8-bit memory offset from address $FF00 specified by C register (last page memory address offset)
• [HL] - 8-bit value at the memory address specified by 16-bit register value HL, where H is the High byte and L is the Low byte
• [HL+] - 8-bit value at memory address specified by 16-bit register value HL, but after performing the instruction, increment HL by 1
• [HL-] - 8-bit value at memory address specified by 16-bit register value HL, but after performing the instruction, decrement HL by 1
• [r16] - 16-bit value at memory address specified by combined register, where the first register is the High byte and the second register is the Low byte (BC, DE, HL)
• [u8] - 8-bit memory address offset from address $FF00 specified by unsigned integer number (last page memory address offset)
• [u16] - 16-bit memory address specified by unsigned integer number (assembly code will use big-endian numbers, machine code will encode the number in little-endian form)

ADC - Add With Cary

Adds target value and Carry Flag (CF) (1 if set or 0 if clear) to source and stores the result in source

Status Flags (F) After Use:

• CF: 1 if result overflowed from bit 7, otherwise 0
• HF: 1 if result overflowed from bit 3, otherwise 0
• NF: 0
• ZF: 1 if result is 0, otherwise 0

ADC A,r8

• Alternative Syntax: ADC r8
• Bytes: 1
• Cycles: 4
• Opcode r8 = A: $8F
• Opcode r8 = B: $88
• Opcode r8 = C: $89
• Opcode r8 = D: $8A
• Opcode r8 = E: $8B
• Opcode r8 = H: $8C
• Opcode r8 = L: $8D

ADC A,[HL]

• Alternative Syntax: ADC [HL]
• Bytes: 1
• Cycles: 8
• Opcode: $8E

ADC A,u8

• Alternative Syntax: ADC u8
• Bytes: 2
• Cycles: 8
• Opcode: $CE

ADD (8-bit) - Add

Adds the A register value and target value together and stores the result in the A register

Status Flags (F) After Use:

• CF: 1 if result overflowed from bit 7, otherwise 0
• HF: 1 if result overflowed from bit 3, otherwise 0
• NF: 0
• ZF: 1 if result is 0, otherwise 0

ADD A,r8

• Alternative Syntax: ADD r8
• Bytes: 1
• Cycles: 4
• Opcode r8 = A: $87
• Opcode r8 = B: $80
• Opcode r8 = C: $81
• Opcode r8 = D: $82
• Opcode r8 = E: $83
• Opcode r8 = H: $84
• Opcode r8 = L: $85

ADD A,[HL]

• Alternative Syntax: ADD [HL]
• Bytes: 1
• Cycles: 8
• Opcode: $86

ADD A,u8

• Alternative Syntax: ADD u8
• Bytes: 2
• Cycles: 8
• Opcode: $C6

ADD (16-bit) - Add

Adds source value and target value together and stores the result in source

Status Flags (F) After Use:

• CF: 1 if result overflowed from bit 15
• HF: 1 if result overflowed from bit 11
• NF: 0
• ZF: -

ADD HL,r16

• Bytes: 1
• Cycles: 8
• Opcode r16 = BC: $09
• Opcode r16 = DE: $19
• Opcode r16 = HL: $29

ADD HL,SP

• Bytes: 1
• Cycles: 8
• Opcode: $39

AND - Logical AND

Performs a logical AND between source value and target value and stores the result in source

Status Flags (F) After Use:

• CF: 0
• HF: 1
• NF: 0
• ZF: 1 if result is 0, otherwise 0

AND A,r8

• Alternative Syntax: AND r8
• Bytes: 1
• Cycles: 4
• Opcode r8 = A: $A7
• Opcode r8 = B: $A0
• Opcode r8 = C: $A1
• Opcode r8 = D: $A2
• Opcode r8 = E: $A3
• Opcode r8 = H: $A4
• Opcode r8 = L: $A5

AND A,[HL]

• Alternative Syntax: AND [HL]
• Bytes: 1
• Cycles: 8
• Opcode: $A6

AND A,u8

• Alternative Syntax: AND u8
• Bytes: 2
• Cycles: 8
• Opcode: $E6

BIT - Test Bit

Test specified bit of target value

Status Flags (F) After Use:

• CF: -
• HF: 1
• NF: 0
• ZF: 1 if specified target bit is 0, otherwise 0

BIT u3,r8

• Bytes: 2
• Cycles: 8
• Opcode u3 = 0, r8 = A: $CB $47
• Opcode u3 = 0, r8 = B: $CB $40
• Opcode u3 = 0, r8 = C: $CB $41
• Opcode u3 = 0, r8 = D: $CB $42
• Opcode u3 = 0, r8 = E: $CB $43
• Opcode u3 = 0, r8 = H: $CB $44
• Opcode u3 = 0, r8 = L: $CB $45
• Opcode u3 = 1, r8 = A: $CB $4F
• Opcode u3 = 1, r8 = B: $CB $48
• Opcode u3 = 1, r8 = C: $CB $49
• Opcode u3 = 1, r8 = D: $CB $4A
• Opcode u3 = 1, r8 = E: $CB $4B
• Opcode u3 = 1, r8 = H: $CB $4C
• Opcode u3 = 1, r8 = L: $CB $4D
• Opcode u3 = 2, r8 = A: $CB $57
• Opcode u3 = 2, r8 = B: $CB $50
• Opcode u3 = 2, r8 = C: $CB $51
• Opcode u3 = 2, r8 = D: $CB $52
• Opcode u3 = 2, r8 = E: $CB $53
• Opcode u3 = 2, r8 = H: $CB $54
• Opcode u3 = 2, r8 = L: $CB $55
• Opcode u3 = 3, r8 = A: $CB $5F
• Opcode u3 = 3, r8 = B: $CB $58
• Opcode u3 = 3, r8 = C: $CB $59
• Opcode u3 = 3, r8 = D: $CB $5A
• Opcode u3 = 3, r8 = E: $CB $5B
• Opcode u3 = 3, r8 = H: $CB $5C
• Opcode u3 = 3, r8 = L: $CB $5D
• Opcode u3 = 4, r8 = A: $CB $67
• Opcode u3 = 4, r8 = B: $CB $60
• Opcode u3 = 4, r8 = C: $CB $61
• Opcode u3 = 4, r8 = D: $CB $62
• Opcode u3 = 4, r8 = E: $CB $63
• Opcode u3 = 4, r8 = H: $CB $64
• Opcode u3 = 4, r8 = L: $CB $65
• Opcode u3 = 5, r8 = A: $CB $6F
• Opcode u3 = 5, r8 = B: $CB $68
• Opcode u3 = 5, r8 = C: $CB $69
• Opcode u3 = 5, r8 = D: $CB $6A
• Opcode u3 = 5, r8 = E: $CB $6B
• Opcode u3 = 5, r8 = H: $CB $6C
• Opcode u3 = 5, r8 = L: $CB $6D
• Opcode u3 = 6, r8 = A: $CB $77
• Opcode u3 = 6, r8 = B: $CB $70
• Opcode u3 = 6, r8 = C: $CB $71
• Opcode u3 = 6, r8 = D: $CB $72
• Opcode u3 = 6, r8 = E: $CB $73
• Opcode u3 = 6, r8 = H: $CB $74
• Opcode u3 = 6, r8 = L: $CB $75
• Opcode u3 = 7, r8 = A: $CB $7F
• Opcode u3 = 7, r8 = B: $CB $78
• Opcode u3 = 7, r8 = C: $CB $79
• Opcode u3 = 7, r8 = D: $CB $7A
• Opcode u3 = 7, r8 = E: $CB $7B
• Opcode u3 = 7, r8 = H: $CB $7C
• Opcode u3 = 7, r8 = L: $CB $7D

BIT u3,[HL]

• Bytes: 2
• Cycles: 16
• Opcode u3 = 0: $CB $46
• Opcode u3 = 1: $CB $4E
• Opcode u3 = 2: $CB $56
• Opcode u3 = 3: $CB $5E
• Opcode u3 = 4: $CB $66
• Opcode u3 = 5: $CB $6E
• Opcode u3 = 6: $CB $76
• Opcode u3 = 7: $CB $7E

CALL - Call Address

Advance Program Counter (PC) to next instruction, then decrement the Stack Pointer (SP), then copy the High byte of the Program Counter (PC) into the address pointed to by the Stack Pointer (SP), then decrement the Stack Pointer (SP) a second time, then copy the Low byte of the Program Counter (PC) into the address pointed to by the Stack Pointer (SP), then set the Program Counter (PC) to target address

Status Flags (F) After Use:

• CF: -
• HF: -
• NF: -
• ZF: -

CALL u16

• Bytes: 3
• Cycles: 24
• Opcode: $CD

CALL cc,u16

• Bytes: 3
• Cycles: 24 (12 if condition not met)
• Opcode cc = C: $DC
• Opcode cc = NC: $D4
• Opcode cc = Z: $CC
• Opcode cc = NZ: $C4

CCF - Complement Carry Flag

Performs a logical NOT of the Carry Flag (CF) and sets the Carry Flag (CF) to the result

Status Flags (F) After Use:

• CF: 1 if original Carry Flag (CF) was clear at start of instruction, otherwise 0
• HF: 0
• NF: 0
• ZF: -

CCF

• Bytes: 1
• Cycles: 4
• Opcode: $3F

CP - Compare A Register

Subtract target value from A register, setting status flags accordingly, but does not store the result

Status Flags (F) After Use:

• CF: 1 if target value is larger than A register value, otherwise 0
• HF: 1 if result borrowed from bit 4, otherwise 0
• NF: 1
• ZF: 1 if result is 0, otherwise 0

CP A,r8

• Alternative Syntax: CP r8
• Bytes: 1
• Cycles: 4
• Opcode r8 = A: $BF
• Opcode r8 = B: $B8
• Opcode r8 = C: $B9
• Opcode r8 = D: $BA
• Opcode r8 = E: $BB
• Opcode r8 = H: $BC
• Opcode r8 = L: $BD

CP A,[HL]

• Alternative Syntax: CP [HL]
• Bytes: 1
• Cycles: 8
• Opcode: $BE

CP A,u8

• Alternative Syntax: CP u8
• Bytes: 2
• Cycles: 8
• Opcode: $FE

CPL - Complement A Register

Performs a logical NOT of the A register and sets the A register to the result

Status Flags (F) After Use:

• CF: -
• HF: 1
• NF: 1
• ZF: -

CPL

• Bytes: 1
• Cycles: 4
• Opcode: $2F

DAA - Decimal Adjust A Register

Converts the A register value to Binary-Coded Decimal (BCD). In essence, if the Negative Flag (NF) was set at the start of this instruction, an adjustment is made by subtracting 6 from each nibble (left and right 4-bit halves of a byte) that is larger than 9, otherwise if the Negative Flag (NF) was clear at the start of this instruction, an adjustment is made by adding 6 to each nibble that is larger than 9.

Status Flags (F) After Use:

• CF: 1 if Negative Flag (NF) and Carry Flag (CF) were both set at the start of the instruction, or 1 if Negative Flag (NF) was clear and adjusting the the result overflowed bit 7, otherwise 0
• HF: -
• NF: 0
• ZF: 1 if result is 0, otherwise 0

DAA

• Bytes: 1
• Cycles: 4
• Opcode: $27

DEC (8-bit) - Decrement Value

Decrement source value by 1 and store the result in source

Status Flags (F) After Use:

• CF: -
• HF: 1 if result borrowed from bit 4, otherwise 0
• NF: 1
• ZF: 1 if result is 0, otherwise 0

DEC r8

• Bytes: 1
• Cycles: 4
• Opcode r8 = A: $3D
• Opcode r8 = B: $05
• Opcode r8 = C: $0D
• Opcode r8 = D: $15
• Opcode r8 = E: $1D
• Opcode r8 = H: $25
• Opcode r8 = L: $2D

DEC [HL]

• Bytes: 1
• Cycles: 12
• Opcode: $35

DEC (16-bit) - Decrement Value

Decrement source value by 1 and store the result in source

Status Flags (F) After Use:

• CF: -
• HF: -
• NF: -
• ZF: -

DEC r16

• Bytes: 1
• Cycles: 8
• Opcode r16 = BC: $0B
• Opcode r16 = DE: $1B
• Opcode r16 = HL: $2B

DEC SP

• Bytes: 1
• Cycles: 8
• Opcode r16 = BC: $3B

DI - Disable Interrupts

Clears Interrupt Master Enable (IME)

Status Flags (F) After Use:

• CF: -
• HF: -
• NF: -
• ZF: -

DI

• Bytes: 1
• Cycles: 4
• Opcode: $F3

EI - Enable Interrupts

Sets Interrupt Master Enable (IME) after the next instruction

Status Flags (F) After Use:

• CF: -
• HF: -
• NF: -
• ZF: -

EI

• Bytes: 1
• Cycles: 4
• Opcode: $FB

HALT - Enter CPU Low-Power Mode

Halt CPU, entering low-power consumption mode until interrupt occurs

Status Flags (F) After Use:

• CF: -
• HF: -
• NF: -
• ZF: -

HALT

• Bytes: 1
• Cycles: 4
• Opcode: $76

INC (8-bit) - Increment Value

Increment source value by 1 and store the result in source

Status Flags (F) After Use:

• CF: -
• HF: 1 if result overflowed from bit 3, otherwise 0
• NF: 0
• ZF: 1 if result is 0, otherwise 0

INC r8

• Bytes: 1
• Cycles: 4
• Opcode r8 = A: $3C
• Opcode r8 = B: $04
• Opcode r8 = C: $0C
• Opcode r8 = D: $14
• Opcode r8 = E: $1C
• Opcode r8 = H: $24
• Opcode r8 = L: $2C

INC [HL]

• Bytes: 1
• Cycles: 12
• Opcode: $34

INC (16-bit) - Increment Value

Increment source value by 1 and store the result in source

Status Flags (F) After Use:

• CF: -
• HF: -
• NF: -
• ZF: -

INC r8

• Bytes: 1
• Cycles: 8
• Opcode r8 = BC: $03
• Opcode r8 = DE: $13
• Opcode r8 = HL: $23

INC SP

• Bytes: 1
• Cycles: 8
• Opcode: $33

JP - Jump to Address

Set Program Counter (PC) to target address

Status Flags (F) After Use:

• CF: -
• HF: -
• NF: -
• ZF: -

JP u16

• Bytes: 3
• Cycles: 16
• Opcode: $C3

JP cc,u16

• Bytes: 3
• Cycles: 16 (12 if condition not met)
• Opcode cc = C: $DA
• Opcode cc = NC: $D2
• Opcode cc = Z: $CA
• Opcode cc = NZ: $C2

JP [HL]

• Bytes: 1
• Cycles: 4
• Opcode: $E9

JR - Jump Relative

Relative jump to target address. While the GBZ80 assembly code uses a 16-bit little-endian address, the machine code uses a signed 8-bit number for the target value (-128 to 127 bytes away from the address following the JR instruction). The target address MUST be within -128 to 127 bytes away from the address following the JR instruction.

Status Flags (F) After Use:

• CF: -
• HF: -
• NF: -
• ZF: -

JR u16

• Bytes: 2
• Cycles: 12
• Opcode: $18

JP cc,u16

• Bytes: 2
• Cycles: 12 (8 if condition not met)
• Opcode cc = C: $38
• Opcode cc = NC: $30
• Opcode cc = Z: $28
• Opcode cc = NZ: $20

LD (8-bit) - Load Value

Copy value from target value and store it into source

Status Flags (F) After Use:

• CF: -
• HF: -
• NF: -
• ZF: -

LD r8,r8

• Bytes: 1
• Cycles: 4
• Opcode first r8 = A, second r8 = A: $7F
• Opcode first r8 = A, second r8 = B: $78
• Opcode first r8 = A, second r8 = C: $79
• Opcode first r8 = A, second r8 = D: $7A
• Opcode first r8 = A, second r8 = E: $7B
• Opcode first r8 = A, second r8 = H: $7C
• Opcode first r8 = A, second r8 = L: $7D
• Opcode first r8 = B, second r8 = A: $47
• Opcode first r8 = B, second r8 = B: $40
• Opcode first r8 = B, second r8 = C: $41
• Opcode first r8 = B, second r8 = D: $42
• Opcode first r8 = B, second r8 = E: $43
• Opcode first r8 = B, second r8 = H: $44
• Opcode first r8 = B, second r8 = L: $45
• Opcode first r8 = C, second r8 = A: $4F
• Opcode first r8 = C, second r8 = B: $48
• Opcode first r8 = C, second r8 = C: $49
• Opcode first r8 = C, second r8 = D: $4A
• Opcode first r8 = C, second r8 = E: $4B
• Opcode first r8 = C, second r8 = H: $4C
• Opcode first r8 = C, second r8 = L: $4D
• Opcode first r8 = D, second r8 = A: $57
• Opcode first r8 = D, second r8 = B: $50
• Opcode first r8 = D, second r8 = C: $51
• Opcode first r8 = D, second r8 = D: $52
• Opcode first r8 = D, second r8 = E: $53
• Opcode first r8 = D, second r8 = H: $54
• Opcode first r8 = D, second r8 = L: $55
• Opcode first r8 = E, second r8 = A: $5F
• Opcode first r8 = E, second r8 = B: $58
• Opcode first r8 = E, second r8 = C: $59
• Opcode first r8 = E, second r8 = D: $5A
• Opcode first r8 = E, second r8 = E: $5B
• Opcode first r8 = E, second r8 = H: $5C
• Opcode first r8 = E, second r8 = L: $5D
• Opcode first r8 = H, second r8 = A: $67
• Opcode first r8 = H, second r8 = B: $60
• Opcode first r8 = H, second r8 = C: $61
• Opcode first r8 = H, second r8 = D: $62
• Opcode first r8 = H, second r8 = E: $63
• Opcode first r8 = H, second r8 = H: $64
• Opcode first r8 = H, second r8 = L: $65
• Opcode first r8 = L, second r8 = A: $6F
• Opcode first r8 = L, second r8 = B: $68
• Opcode first r8 = L, second r8 = C: $69
• Opcode first r8 = L, second r8 = D: $6A
• Opcode first r8 = L, second r8 = E: $6B
• Opcode first r8 = L, second r8 = H: $6C
• Opcode first r8 = L, second r8 = L: $6D

LD r8,u8

• Bytes: 2
• Cycles: 8
• Opcode r8 = A: $3E
• Opcode r8 = B: $06
• Opcode r8 = C: $0E
• Opcode r8 = D: $16
• Opcode r8 = E: $1E
• Opcode r8 = H: $26
• Opcode r8 = L: $2E

LD [HL],r8

• Bytes: 1
• Cycles: 8
• Opcode r8 = A: $77
• Opcode r8 = B: $70
• Opcode r8 = C: $71
• Opcode r8 = D: $72
• Opcode r8 = E: $73
• Opcode r8 = H: $74
• Opcode r8 = L: $75

LD [HL],u8

• Bytes: 2
• Cycles: 12
• Opcode: $36

LD r8,[HL]

• Bytes: 1
• Cycles: 8
• Opcode r8 = A: $7E
• Opcode r8 = B: $46
• Opcode r8 = C: $4E
• Opcode r8 = D: $56
• Opcode r8 = E: $5E
• Opcode r8 = H: $66
• Opcode r8 = L: $6E

LD [r16],A

• Bytes: 1
• Cycles: 8
• Opcode r8 = BC: $02
• Opcode r8 = DE: $12
• Opcode r8 = HL: $77

LD [u16],A

• Bytes: 3
• Cycles: 16
• Opcode: $EA

LD A,[r16]

• Bytes: 1
• Cycles: 8
• Opcode r16 = BC: $0A
• Opcode r16 = DE: $1A
• Opcode r16 = HL: $7E

LD A,[u16]

• Bytes: 3
• Cycles: 16
• Opcode: $FA

LD [HL+],A

• Bytes: 1
• Cycles: 8
• Opcode: $22

LD [HL-],A

• Bytes: 1
• Cycles: 8
• Opcode: $32

LD A,[HL+]

• Bytes: 1
• Cycles: 8
• Opcode: $2A

LD A,[HL-]

• Bytes: 1
• Cycles: 8
• Opcode: $3A

LD (16-bit) - Load Value

Copy value from target value and store it into source

Status Flags (F) After Use:

• CF: -
• HF: -
• NF: -
• ZF: -

LD r16,u16

• Bytes: 3
• Cycles: 12
• Opcode r8 = BC: $01
• Opcode r8 = DE: $11
• Opcode r8 = HL: $21

LD SP,u16

• Bytes: 3
• Cycles: 12
• Opcode: $31

LD [u16],SP

• Bytes: 3
• Cycles: 12
• Opcode: $08

LD SP,[HL]

• Bytes: 1
• Cycles: 8
• Opcode: $F9

LD (Misc. 1) - Load Value

Copy the Low byte value of the Stack Pointer (SP) and store it into source address, then copy the High byte of the Stack Pointer (SP) and store it into source address + 1

Status Flags (F) After Use:

• CF: -
• HF: -
• NF: -
• ZF: -

LD [u16],SP

• Bytes: 3
• Cycles: 20
• Opcode: $08

LD (Misc. 2) - Load Value

Copy the value of the Stack Pointer, add a specified signed byte to it, and store the result into the HL combined register

Status Flags (F) After Use:

• CF: 1 if result overflowed from bit 7, otherwise 0
• HF: 1 if result overflowed from bit 3, otherwise 0
• NF: 0
• ZF: 0

LD HL,SP+s8

• Bytes: 2
• Cycles: 12
• Opcode: $F8

LDH - Load With Last Page

Copy value from target value and store it into source

Status Flags (F) After Use:

• CF: -
• HF: -
• NF: -
• ZF: -

LDH [u8],A

• Alternative Syntax: LDH [$FF00+u8],A
• Bytes: 2
• Cycles: 12
• Opcode: $E0

LDH [C],A

• Alternative Syntax: LDH [$FF00+C],A
• Bytes: 1
• Cycles: 8
• Opcode: $E2

LDH A,[u8]

• Alternative Syntax: LDH A,[$FF00+u8]
• Bytes: 2
• Cycles: 12
• Opcode: $F0

LDH A,[C]

• Alternative Syntax: LDH A,[$FF00+C]
• Bytes: 1
• Cycles: 8
• Opcode: $F2

NOP - No Operation

No operation occurs (Good way to use up CPU cycles)

Status Flags (F) After Use:

• CF: -
• HF: -
• NF: -
• ZF: -

NOP

• Bytes: 1
• Cycles: 4
• Opcode: $00

OR - Logical OR

Performs a logical OR between source value and target value and stores the result in source

Status Flags (F) After Use:

• CF: 0
• HF: 0
• NF: 0
• ZF: 1 if result is 0, otherwise 0

OR A,r8

• Alternative Syntax: OR r8
• Bytes: 1
• Cycles: 4
• Opcode r8 = A: $B7
• Opcode r8 = B: $B0
• Opcode r8 = C: $B1
• Opcode r8 = D: $B2
• Opcode r8 = E: $B3
• Opcode r8 = H: $B4
• Opcode r8 = L: $B5

OR A,[HL]

• Alternative Syntax: OR [HL]
• Bytes: 1
• Cycles: 8
• Opcode: $B6

OR A,u8

• Alternative Syntax: OR u8
• Bytes: 2
• Cycles: 8
• Opcode: $F6

POP - Pop Value From Stack

Copy the value at the address pointed to by the Stack Pointer (SP) into the Low byte of the combined-register, then increment the Stack Pointer (SP), then copy the value at the address pointed to by the Stack Pointer (SP) into the High byte of the combined-register, then increment the Stack Pointer (SP) a second time

Status Flags (F) After Use:

• CF: -
• HF: -
• NF: -
• ZF: -

POP r16

• Bytes: 1
• Cycles: 12
• Opcode r16 = BC: $C1
• Opcode r16 = DE: $D1
• Opcode r16 = HL: $E1

POP (AF) - Pop Value From Stack

Copy the value at the address pointed to by the Stack Pointer (SP) into Status Flags (F), then increment the Stack Pointer (SP), then copy the value at the address pointed to by the Stack Pointer (SP) into the A register, then increment the Stack Pointer (SP) a second time

Status Flags (F) After Use:

• CF: 1 if bit 4 of first copied byte is 1, otherwise 0
• HF: 1 if bit 5 of first copied byte is 1, otherwise 0
• NF: 1 if bit 6 of first copied byte is 1, otherwise 0
• ZF: 1 if bit 7 of first copied byte is 1, otherwise 0

POP AF

• Bytes: 1
• Cycles: 12
• Opcode: $F1

PUSH - Push Value to Stack

Decrement the Stack Pointer (SP), then copy the High byte of the combined-register value into the address pointed to by the Stack Pointer (SP), then decrement the Stack Pointer (SP) a second time, then copy the Low byte of the combined-register value into the address pointed to by the Stack Pointer (SP)

Status Flags (F) After Use:

• CF: -
• HF: -
• NF: -
• ZF: -

PUSH r16

• Bytes: 1
• Cycles: 16
• Opcode r16 = BC: $C5
• Opcode r16 = DE: $D5
• Opcode r16 = HL: $E5

PUSH AF

• Bytes: 1
• Cycles: 16
• Opcode: $F5

RES - Clear Bit

Clear (set value to 0) specified bit of target value

Status Flags (F) After Use:

• CF: -
• HF: -
• NF: -
• ZF: -

RES u3,r8

• Bytes: 2
• Cycles: 8
• Opcode u3 = 0, r8 = A: $CB $87
• Opcode u3 = 0, r8 = B: $CB $80
• Opcode u3 = 0, r8 = C: $CB $81
• Opcode u3 = 0, r8 = D: $CB $82
• Opcode u3 = 0, r8 = E: $CB $83
• Opcode u3 = 0, r8 = H: $CB $84
• Opcode u3 = 0, r8 = L: $CB $85
• Opcode u3 = 1, r8 = A: $CB $8F
• Opcode u3 = 1, r8 = B: $CB $88
• Opcode u3 = 1, r8 = C: $CB $89
• Opcode u3 = 1, r8 = D: $CB $8A
• Opcode u3 = 1, r8 = E: $CB $8B
• Opcode u3 = 1, r8 = H: $CB $8C
• Opcode u3 = 1, r8 = L: $CB $8D
• Opcode u3 = 2, r8 = A: $CB $97
• Opcode u3 = 2, r8 = B: $CB $90
• Opcode u3 = 2, r8 = C: $CB $91
• Opcode u3 = 2, r8 = D: $CB $92
• Opcode u3 = 2, r8 = E: $CB $93
• Opcode u3 = 2, r8 = H: $CB $94
• Opcode u3 = 2, r8 = L: $CB $95
• Opcode u3 = 3, r8 = A: $CB $9F
• Opcode u3 = 3, r8 = B: $CB $98
• Opcode u3 = 3, r8 = C: $CB $99
• Opcode u3 = 3, r8 = D: $CB $9A
• Opcode u3 = 3, r8 = E: $CB $9B
• Opcode u3 = 3, r8 = H: $CB $9C
• Opcode u3 = 3, r8 = L: $CB $9D
• Opcode u3 = 4, r8 = A: $CB $A7
• Opcode u3 = 4, r8 = B: $CB $A0
• Opcode u3 = 4, r8 = C: $CB $A1
• Opcode u3 = 4, r8 = D: $CB $A2
• Opcode u3 = 4, r8 = E: $CB $A3
• Opcode u3 = 4, r8 = H: $CB $A4
• Opcode u3 = 4, r8 = L: $CB $A5
• Opcode u3 = 5, r8 = A: $CB $AF
• Opcode u3 = 5, r8 = B: $CB $A8
• Opcode u3 = 5, r8 = C: $CB $A9
• Opcode u3 = 5, r8 = D: $CB $AA
• Opcode u3 = 5, r8 = E: $CB $AB
• Opcode u3 = 5, r8 = H: $CB $AC
• Opcode u3 = 5, r8 = L: $CB $AD
• Opcode u3 = 6, r8 = A: $CB $B7
• Opcode u3 = 6, r8 = B: $CB $B0
• Opcode u3 = 6, r8 = C: $CB $B1
• Opcode u3 = 6, r8 = D: $CB $B2
• Opcode u3 = 6, r8 = E: $CB $B3
• Opcode u3 = 6, r8 = H: $CB $B4
• Opcode u3 = 6, r8 = L: $CB $B5
• Opcode u3 = 7, r8 = A: $CB $BF
• Opcode u3 = 7, r8 = B: $CB $B8
• Opcode u3 = 7, r8 = C: $CB $B9
• Opcode u3 = 7, r8 = D: $CB $BA
• Opcode u3 = 7, r8 = E: $CB $BB
• Opcode u3 = 7, r8 = H: $CB $BC
• Opcode u3 = 7, r8 = L: $CB $BD

RES u3,[HL]

• Bytes: 2
• Cycles: 16
• Opcode u3 = 0: $CB $86
• Opcode u3 = 1: $CB $8E
• Opcode u3 = 2: $CB $96
• Opcode u3 = 3: $CB $9E
• Opcode u3 = 4: $CB $A6
• Opcode u3 = 5: $CB $AE
• Opcode u3 = 6: $CB $B6
• Opcode u3 = 7: $CB $BE

RET - Return From Subroutine

Copy the value at the address pointed to by the Stack Pointer (SP) into the Low byte of the Program Counter (PC), then increment the Stack Pointer (SP), then copy the value at the address pointed to by the Stack Pointer (SP) into the High byte of the Program Counter (PC), then increment the Stack Pointer (SP) a second time

Status Flags (F) After Use:

• CF: -
• HF: -
• NF: -
• ZF: -

RET

• Bytes: 1
• Cycles: 16
• Opcode: $C9

RET cc

• Bytes: 1
• Cycles: 20 (8 if condition not met)
• Opcode cc = C: $D8
• Opcode cc = NC: $D0
• Opcode cc = Z: $C8
• Opcode cc = NZ: $C0

RETI - Return From Subroutine Enable Interrupts

Copy the value at the address pointed to by the Stack Pointer (SP) into the Low byte of the Program Counter (PC), then increment the Stack Pointer (SP), then copy the value at the address pointed to by the Stack Pointer (SP) into the High byte of the Program Counter (PC), then increment the Stack Pointer (SP) a second time, then sets Interrupt Master Enable (IME)

Status Flags (F) After Use:

• CF: -
• HF: -
• NF: -
• ZF: -

RETI

• Bytes: 1
• Cycles: 16
• Opcode: $D9

RL - Rotate Left Through Carry Flag

Shift every bit of source left 1, setting bit 0 of the result to the value of the Carry Flag (CF) (1 if set or 0 if clear) and then setting the Carry Flag (CF) to bit 7 of the source, then store the result in source

Status Flags (F) After Use:

• CF: 1 if bit 7 of original source value was 1, otherwise 0
• HF: 0
• NF: 0
• ZF: 1 if result is 0, otherwise 0

RL r8

• Bytes: 2
• Cycles: 8
• Opcode r8 = A: $CB $17
• Opcode r8 = B: $CB $10
• Opcode r8 = C: $CB $11
• Opcode r8 = D: $CB $12
• Opcode r8 = E: $CB $13
• Opcode r8 = H: $CB $14
• Opcode r8 = L: $CB $15

RL [HL]

• Bytes: 2
• Cycles: 16
• Opcode: $CB $16

RLA - Rotate A Register Left Through Carry Flag

Shift every bit of the A register left 1, setting bit 0 of the result to the value of the Carry Flag (CF) (1 if set or 0 if clear) and then setting the Carry Flag (CF) to bit 7 of the A register, then store the result in the A register

Status Flags (F) After Use:

• CF: 1 if bit 7 of original A register value was 1, otherwise 0
• HF: 0
• NF: 0
• ZF: 0

RLA

• Bytes: 1
• Cycles: 4
• Opcode: $17

RLC - Rotate Left

Shift every bit of source left 1, setting bit 0 of the result to bit 7 of the source and then setting the Carry Flag (CF) to the bit 7 of the source, then store the result in source

Status Flags (F) After Use:

• CF: 1 if bit 7 of original source value was 1, otherwise 0
• HF: 0
• NF: 0
• ZF: 1 if result is 0, otherwise 0

RLC r8

• Bytes: 2
• Cycles: 8
• Opcode r8 = A: $CB $07
• Opcode r8 = B: $CB $00
• Opcode r8 = C: $CB $01
• Opcode r8 = D: $CB $02
• Opcode r8 = E: $CB $03
• Opcode r8 = H: $CB $04
• Opcode r8 = L: $CB $05

RLC [HL]

• Bytes: 2
• Cycles: 16
• Opcode: $CB $06

RLCA - Rotate A Register Left

Shift every bit of the A register left 1, setting bit 0 of the result to bit 7 of the A register and then setting the Carry Flag (CF) to the bit 7 of the A register, then store the result in the A register

Status Flags (F) After Use:

• CF: 1 if bit 7 of original A register value was 1, otherwise 0
• HF: 0
• NF: 0
• ZF: 0

RLCA

• Bytes: 1
• Cycles: 4
• Opcode: $07

RR - Rotate Right Through Carry Flag

Shift every bit of source right 1, setting bit 7 of the result to the value of the Carry Flag (CF) (1 if set or 0 if clear) and then setting the Carry Flag (CF) to bit 0 of the source, then store the result in source

Status Flags (F) After Use:

• CF: 1 if bit 0 of original source value was 1, otherwise 0
• HF: 0
• NF: 0
• ZF: 1 if result is 0, otherwise 0

RR r8

• Bytes: 2
• Cycles: 8
• Opcode r8 = A: $CB $1F
• Opcode r8 = B: $CB $18
• Opcode r8 = C: $CB $19
• Opcode r8 = D: $CB $1A
• Opcode r8 = E: $CB $1B
• Opcode r8 = H: $CB $1C
• Opcode r8 = L: $CB $1D

RR [HL]

• Bytes: 2
• Cycles: 16
• Opcode: $CB $1E

RRA - Rotate A Register Right Through Carry Flag

Shift every bit of the A register right 1, setting bit 7 of the result to the value of the Carry Flag (CF) (1 if set or 0 if clear) and then setting the Carry Flag (CF) to bit 0 of the A register, then store the result in the A register

Status Flags (F) After Use:

• CF: 1 if bit 0 of original A register value was 1, otherwise 0
• HF: 0
• NF: 0
• ZF: 0

RRA

• Bytes: 1
• Cycles: 4
• Opcode: $1F

RRC - Rotate Right

Shift every bit of source right 1, setting bit 7 of the result to bit 0 of the source and then setting the Carry Flag (CF) to the bit 0 of the source, then store the result in source

Status Flags (F) After Use:

• CF: 1 if bit 0 of original source value was 1, otherwise 0
• HF: 0
• NF: 0
• ZF: 1 if result is 0, otherwise 0

RRC r8

• Bytes: 2
• Cycles: 8
• Opcode r8 = A: $CB $0F
• Opcode r8 = B: $CB $08
• Opcode r8 = C: $CB $09
• Opcode r8 = D: $CB $0A
• Opcode r8 = E: $CB $0B
• Opcode r8 = H: $CB $0C
• Opcode r8 = L: $CB $0D

RRC [HL]

• Bytes: 2
• Cycles: 16
• Opcode: $CB $0E

RRCA - Rotate A Register Right

Shift every bit of the A register right 1, setting bit 7 of the result to bit 0 of the A register and then setting the Carry Flag (CF) to the bit 0 of the A register, then store the result in the A register

Status Flags (F) After Use:

• CF: 1 if bit 0 of original A register value was 1, otherwise 0
• HF: 0
• NF: 0
• ZF: 0

RRCA

• Bytes: 1
• Cycles: 4
• Opcode: $0F

RST - Reset Vector

Advance Program Counter (PC) to next instruction, then decrement the Stack Pointer (SP), then copy the High byte of the Program Counter (PC) into the address pointed to by the Stack Pointer (SP), then decrement the Stack Pointer (SP) a second time, then copy the Low byte of the Program Counter (PC) into the address pointed to by the Stack Pointer (SP), then set the Program Counter (PC) to [$0000 + target reset vector]

Status Flags (F) After Use:

• CF: -
• HF: -
• NF: -
• ZF: -

RST vec

• Bytes: 1
• Cycles: 16
• Opcode vec = $00: $C7
• Opcode vec = $08: $CF
• Opcode vec = $10: $D7
• Opcode vec = $18: $DF
• Opcode vec = $20: $E7
• Opcode vec = $28: $EF
• Opcode vec = $30: $F7
• Opcode vec = $38: $FF

SBC - Subtract With Carry

Subtracts target value and Carry Flag (CF) (1 if set or 0 if clear) from the A register and stores the result in the A register

Status Flags (F) After Use:

• CF: 1 if target value and original Carry Flag (CF) (1 if set or 0 if clear) combined are larger than A register value, otherwise 0
• HF: 1 if result borrowed from bit 4, otherwise 0
• NF: 1
• ZF: 1 if result is 0, otherwise 0

SBC A,r8

• Alternative Syntax: SBC r8
• Bytes: 1
• Cycles: 4
• Opcode r8 = A: $9F
• Opcode r8 = B: $98
• Opcode r8 = C: $99
• Opcode r8 = D: $9A
• Opcode r8 = E: $9B
• Opcode r8 = H: $9C
• Opcode r8 = L: $9D

SBC A,[HL]

• Alternative Syntax: SBC [HL]
• Bytes: 1
• Cycles: 8
• Opcode: $9E

SBC A,u8

• Alternative Syntax: SBC u8
• Bytes: 2
• Cycles: 8
• Opcode: $DE

SCF - Set Carry Flag

Sets the Carry Flag (CF)

Status Flags (F) After Use:

• CF: 1
• HF: 0
• NF: 0
• ZF: -

SCF

• Bytes: 1
• Cycles: 4
• Opcode: $37

SET - Set Bit

Set (set value to 1) specified bit of target value

Status Flags (F) After Use:

• CF: -
• HF: -
• NF: -
• ZF: -

SET u3,r8

• Bytes: 2
• Cycles: 8
• Opcode u3 = 0, r8 = A: $CB $C7
• Opcode u3 = 0, r8 = B: $CB $C0
• Opcode u3 = 0, r8 = C: $CB $C1
• Opcode u3 = 0, r8 = D: $CB $C2
• Opcode u3 = 0, r8 = E: $CB $C3
• Opcode u3 = 0, r8 = H: $CB $C4
• Opcode u3 = 0, r8 = L: $CB $C5
• Opcode u3 = 1, r8 = A: $CB $CF
• Opcode u3 = 1, r8 = B: $CB $C8
• Opcode u3 = 1, r8 = C: $CB $C9
• Opcode u3 = 1, r8 = D: $CB $CA
• Opcode u3 = 1, r8 = E: $CB $CB
• Opcode u3 = 1, r8 = H: $CB $CC
• Opcode u3 = 1, r8 = L: $CB $CD
• Opcode u3 = 2, r8 = A: $CB $D7
• Opcode u3 = 2, r8 = B: $CB $D0
• Opcode u3 = 2, r8 = C: $CB $D1
• Opcode u3 = 2, r8 = D: $CB $D2
• Opcode u3 = 2, r8 = E: $CB $D3
• Opcode u3 = 2, r8 = H: $CB $D4
• Opcode u3 = 2, r8 = L: $CB $D5
• Opcode u3 = 3, r8 = A: $CB $DF
• Opcode u3 = 3, r8 = B: $CB $D8
• Opcode u3 = 3, r8 = C: $CB $D9
• Opcode u3 = 3, r8 = D: $CB $DA
• Opcode u3 = 3, r8 = E: $CB $DB
• Opcode u3 = 3, r8 = H: $CB $DC
• Opcode u3 = 3, r8 = L: $CB $DD
• Opcode u3 = 4, r8 = A: $CB $E7
• Opcode u3 = 4, r8 = B: $CB $E0
• Opcode u3 = 4, r8 = C: $CB $E1
• Opcode u3 = 4, r8 = D: $CB $E2
• Opcode u3 = 4, r8 = E: $CB $E3
• Opcode u3 = 4, r8 = H: $CB $E4
• Opcode u3 = 4, r8 = L: $CB $E5
• Opcode u3 = 5, r8 = A: $CB $EF
• Opcode u3 = 5, r8 = B: $CB $E8
• Opcode u3 = 5, r8 = C: $CB $E9
• Opcode u3 = 5, r8 = D: $CB $EA
• Opcode u3 = 5, r8 = E: $CB $EB
• Opcode u3 = 5, r8 = H: $CB $EC
• Opcode u3 = 5, r8 = L: $CB $ED
• Opcode u3 = 6, r8 = A: $CB $F7
• Opcode u3 = 6, r8 = B: $CB $F0
• Opcode u3 = 6, r8 = C: $CB $F1
• Opcode u3 = 6, r8 = D: $CB $F2
• Opcode u3 = 6, r8 = E: $CB $F3
• Opcode u3 = 6, r8 = H: $CB $F4
• Opcode u3 = 6, r8 = L: $CB $F5
• Opcode u3 = 7, r8 = A: $CB $FF
• Opcode u3 = 7, r8 = B: $CB $F8
• Opcode u3 = 7, r8 = C: $CB $F9
• Opcode u3 = 7, r8 = D: $CB $FA
• Opcode u3 = 7, r8 = E: $CB $FB
• Opcode u3 = 7, r8 = H: $CB $FC
• Opcode u3 = 7, r8 = L: $CB $FD

SET u3,[HL]

• Bytes: 2
• Cycles: 16
• Opcode u3 = 0: $CB $C6
• Opcode u3 = 1: $CB $CE
• Opcode u3 = 2: $CB $D6
• Opcode u3 = 3: $CB $DE
• Opcode u3 = 4: $CB $E6
• Opcode u3 = 5: $CB $EE
• Opcode u3 = 6: $CB $F6
• Opcode u3 = 7: $CB $FE

SLA - Arithmetic Shift Left

Shift every bit of source left 1, setting bit 0 of the result to 0 and then setting the Carry Flag (CF) to the bit 7 of the source, then store the result in source

Status Flags (F) After Use:

• CF: 1 if bit 7 of original source value was 1, otherwise 0
• HF: 0
• NF: 0
• ZF: 1 if result is 0, otherwise 0

SLA r8

• Bytes: 2
• Cycles: 8
• Opcode r8 = A: $CB $27
• Opcode r8 = B: $CB $20
• Opcode r8 = C: $CB $21
• Opcode r8 = D: $CB $22
• Opcode r8 = E: $CB $23
• Opcode r8 = H: $CB $24
• Opcode r8 = L: $CB $25

SLA [HL]

• Bytes: 2
• Cycles: 16
• Opcode: $CB $26

SRA - Arithmetic Shift Right

Shift every bit of source right 1, setting bit 7 of the result to bit 7 of the source and then setting the Carry Flag (CF) to the bit 0 of the source, then store the result in source

Status Flags (F) After Use:

• CF: 1 if bit 0 of original source value was 1, otherwise 0
• HF: 0
• NF: 0
• ZF: 1 if result is 0, otherwise 0

SRA r8

• Bytes: 2
• Cycles: 8
• Opcode r8 = A: $CB $2F
• Opcode r8 = B: $CB $28
• Opcode r8 = C: $CB $29
• Opcode r8 = D: $CB $2A
• Opcode r8 = E: $CB $2B
• Opcode r8 = H: $CB $2C
• Opcode r8 = L: $CB $2D

SRA [HL]

• Bytes: 2
• Cycles: 16
• Opcode: $CB $2E

SRL - Logical Shift Right

Shift every bit of source right 1, setting bit 7 of the result to 0 and then setting the Carry Flag (CF) to the bit 0 of the source, then store the result in source

Status Flags (F) After Use:

• CF: 1 if bit 0 of original source value was 1, otherwise 0
• HF: 0
• NF: 0
• ZF: 1 if result is 0, otherwise 0

SRL r8

• Bytes: 2
• Cycles: 8
• Opcode r8 = A: $CB $3F
• Opcode r8 = B: $CB $38
• Opcode r8 = C: $CB $39
• Opcode r8 = D: $CB $3A
• Opcode r8 = E: $CB $3B
• Opcode r8 = H: $CB $3C
• Opcode r8 = L: $CB $3D

SRL [HL]

• Bytes: 2
• Cycles: 16
• Opcode: $CB $3E

STOP - Enter CPU Very Low-Power Mode

Halts CPU, entering very low-power consumption mode until any of bits 0-3 of P1/JOY [$FF00] which means the P1 register should be enabled by setting bit 4 or 5 of P1/JOY [$FF00] to 1 before executing a STOP command if the intention is to put the CPU in very low-power mode. IT IS RECOMMENDED NOT TO USE THIS INSTRUCTION FOR ITS HALTING PURPOSE, AS IT BEHAVES UNEXPECTEDLY ON GAME BOY HARDWARE. This instruction is also be used to toggle double speed mode on the CGB by setting bit 0 of KEY1 [$FF4D] to 1 before executing the STOP instruction.

Status Flags (F) After Use:

• CF: -
• HF: -
• NF: -
• ZF: -

STOP $00

• Alternative Syntax: STOP
• Bytes: 2
• Cycles: 4
• Opcode: $10

SUB - Subtract

Subtracts target value from the A register and stores the result in the A register

Status Flags (F) After Use:

• CF: 1 if target value is larger than A register value, otherwise 0
• HF: 1 if result borrowed from bit 4, otherwise 0
• NF: 1
• ZF: 1 if result is 0, otherwise 0

SUB A,r8

• Alternative Syntax: SUB r8
• Bytes: 1
• Cycles: 4
• Opcode r8 = A: $97
• Opcode r8 = B: $90
• Opcode r8 = C: $91
• Opcode r8 = D: $92
• Opcode r8 = E: $93
• Opcode r8 = H: $94
• Opcode r8 = L: $95

SUB A,[HL]

• Alternative Syntax: SUB [HL]
• Bytes: 1
• Cycles: 8
• Opcode: $96

SUB A,u8

• Alternative Syntax: SUB u8
• Bytes: 2
• Cycles: 8
• Opcode: $D6

SWAP - Swap Nibbles

Swap each nibble (left and right 4-bit halves of a byte) of source value and store the result in source

Status Flags (F) After Use:

• CF: 0
• HF: 0
• NF: 0
• ZF: 1 if result is 0, otherwise 0

SWAP r8

• Bytes: 2
• Cycles: 8
• Opcode r8 = A: $CB $37
• Opcode r8 = B: $CB $30
• Opcode r8 = C: $CB $31
• Opcode r8 = D: $CB $32
• Opcode r8 = E: $CB $33
• Opcode r8 = H: $CB $34
• Opcode r8 = L: $CB $35

SWAP [HL]

• Bytes: 2
• Cycles: 16
• Opcode: $CB $36

XOR - Logical XOR (Exclusive OR)

Performs a logical XOR (Exclusive OR) between source value and target value and stores the result in source

Status Flags (F) After Use:

• CF: 0
• HF: 0
• NF: 0
• ZF: 1 if result is 0, otherwise 0

XOR A,r8

• Alternative Syntax: XOR r8
• Bytes: 1
• Cycles: 4
• Opcode r8 = A: $AF
• Opcode r8 = B: $A8
• Opcode r8 = C: $A9
• Opcode r8 = D: $AA
• Opcode r8 = E: $AB
• Opcode r8 = H: $AC
• Opcode r8 = L: $AD

XOR A,[HL]

• Alternative Syntax: XOR [HL]
• Bytes: 1
• Cycles: 8
• Opcode: $AE

XOR A,u8

• Alternative Syntax: XOR u8
• Bytes: 2
• Cycles: 8
• Opcode: $EE

GBZ80 Opcodes Table

       0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0x0_ |NOP | LD | LD |INC |INC |DEC | LD |RCLA| LD |ADD | LD |DEC |INC |DEC | LD |RRCA|
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0x1_ |STOP| LD | LD |INC |INC |DEC | LD |RLA | JR |ADD | LD |DEC |INC |DEC | LD |RRA |
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0x2_ | JR | LD | LD |INC |INC |DEC | LD |DAA | JR |ADD | LD |DEC |INC |DEC | LD |CPL |
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0x3_ | JR | LD | LD |INC |INC |DEC | LD |SCF | JR |ADD | LD |DEC |INC |DEC | LD |CCF |
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0x4_ | LD | LD | LD | LD | LD | LD | LD | LD | LD | LD | LD | LD | LD | LD | LD | LD |
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0x5_ | LD | LD | LD | LD | LD | LD | LD | LD | LD | LD | LD | LD | LD | LD | LD | LD |
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0x6_ | LD | LD | LD | LD | LD | LD | LD | LD | LD | LD | LD | LD | LD | LD | LD | LD |
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0x7_ | LD | LD | LD | LD | LD | LD |HALT| LD | LD | LD | LD | LD | LD | LD | LD | LD |
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0x8_ |ADD |ADD |ADD |ADD |ADD |ADD |ADD |ADD |ADC |ADC |ADC |ADC |ADC |ADC |ADC |ADC |
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0x9_ |SUB |SUB |SUB |SUB |SUB |SUB |SUB |SUB |SBC |SBC |SBC |SBC |SBC |SBC |SBC |SBC |
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0xA_ |AND |AND |AND |AND |AND |AND |AND |AND |XOR |XOR |XOR |XOR |XOR |XOR |XOR |XOR |
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0xB_ | OR | OR | OR | OR | OR | OR | OR | OR | CP | CP | CP | CP | CP | CP | CP | CP |
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0xC_ |RET |POP | JP | JP |CALL|PUSH|ADD |RST |RET |RET | JP |0xCB|CALL|CALL|ADC |RST |
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0xD_ |RET |POP | JP |    |CALL|PUSH|SUB |RST |RET |RETI| JP |    |CALL|    |SBC |RST |
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0xE_ |LDH |POP | LD |    |    |PUSH|AND |RST |ADD | JP | LD |    |    |    |XOR |RST |
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0xF_ |LDH |POP | LD | DI |    |PUSH| OR |RST | LD | LD | LD | EI |    |    | CP |RST |
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+

Prefix 0xCB
       0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0x0_ |RLC |RLC |RLC |RLC |RLC |RLC |RLC |RLC |RRC |RRC |RRC |RRC |RRC |RRC |RRC |RRC |
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0x1_ | RL | RL | RL | RL | RL | RL | RL | RL | RR | RR | RR | RR | RR | RR | RR | RR |
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0x2_ |SLA |SLA |SLA |SLA |SLA |SLA |SLA |SLA |SRA |SRA |SRA |SRA |SRA |SRA |SRA |SRA |
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0x3_ |SWAP|SWAP|SWAP|SWAP|SWAP|SWAP|SWAP|SWAP|SRL |SRL |SRL |SRL |SRL |SRL |SRL |SRL |
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0x4_ |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0x5_ |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0x6_ |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0x7_ |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |BIT |
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0x8_ |RES |RES |RES |RES |RES |RES |RES |RES |RES |RES |RES |RES |RES |RES |RES |RES |
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0x9_ |RES |RES |RES |RES |RES |RES |RES |RES |RES |RES |RES |RES |RES |RES |RES |RES |
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0xA_ |RES |RES |RES |RES |RES |RES |RES |RES |RES |RES |RES |RES |RES |RES |RES |RES |
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0xB_ |RES |RES |RES |RES |RES |RES |RES |RES |RES |RES |RES |RES |RES |RES |RES |RES |
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0xC_ |SET |SET |SET |SET |SET |SET |SET |SET |SET |SET |SET |SET |SET |SET |SET |SET |
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0xD_ |SET |SET |SET |SET |SET |SET |SET |SET |SET |SET |SET |SET |SET |SET |SET |SET |
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0xE_ |SET |SET |SET |SET |SET |SET |SET |SET |SET |SET |SET |SET |SET |SET |SET |SET |
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+
0xF_ |SET |SET |SET |SET |SET |SET |SET |SET |SET |SET |SET |SET |SET |SET |SET |SET |
     +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+

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